Digital Amplifier IC
 Digital Amplifier Module
 Wireless Speaker
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 SMPS
 DSP Application
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Digital audio signal processing algorithm developments and licensing
 
NeoFidelity proprietary 3D surround algorithm
    SRS style 3D surround (no pre-encoding required)
    Advanced feedback cancellation
    Superior sound source localization control
    Simple and light - optimized for minimum computing power condition
 
NeoFidelity proprietary virtual sound field processing
    Any combination of 2/5/6/8 channel input and 2/3/4/5/6/7/8 channel output is possible
    Variety sound field mode (hall, stadium, church...etc)
    Realistic modeling of early relection and natural reverberation
    User-friendly controllable parameters
    Well suited to internal or external memory use
 
Other algorithms
    Graphic/Parametric EQ
    Tone control
    Loudness control
    DRC(Dynamic range compression and expansion)
    AGC(Adaptive gain control)
    Loudspeaker distortion canceller
    Various sound effects such as echo, chorus, phaser, etc
 
DSP Hardware platform design
 
Available audio functions
    I/O Drivers using DSP/BIOS SIO
    Standard Decoder Algorithms
     - Dolby Digital 5.1
     - Digital Theater Sound DTS 5.1/ES Discrete/9624
     - MPEG-2 AAC
     - Noise Generator
    Standard ASP Algorithms:
     - Dolby Pro Logic I/II
     - Dolby Digital EX
     - Dolby Headphone/Virtualizer
     - DTS ES Matrix/Neo:6
     - THX Ultra/Ultra 2
     - Delay Management, Volume Control
     - Bass Management
     - FIL : filter building blocks (FIR/IIR)
    Encoding Algorithms:
     - PCM
AVR platform features
    Device Input
     - Infrared remote-control sensor
     - Rotary encoder& push buttons
    LCD
     - Display status information
    Video
     - OSD
     - Video Switch
    Audio Input
     - Analog In
     - Digital In: S/PDIF
     - Audio Output
     - Line analog out
     - Speaker out
     - Digital out: S/PDIF
 
< Using DSP AVR platform design >
 
TI DSP design house
 
Technical support
    Digital audio processing algorithm design
    Full digital amplifier processor design
    Digital amplifier module design
    Digital audio related system design
 
Cost vs. performance
 
 
DA6x Series Compare Table
 
  DA610 DA601 DA607 DA605
  225mhz 180mhz 180mhz 180mhz
EMIF Clk 100mhz 100mhz 75mhz N/A
EMIF bus width 32/16(QFP) 32/16(QFP) 8 0
ROM 512KB 512KB 512KB 512KB
RAM 256KB 128KB 160KB 160KB
Mem Arch L1/L2 L1/L2 L1/L2 L1/L2
McASP 2(w/DIT) 2(w/DIT) 2(w/DIT) 2(w/DIT)
McASP Data Pins 16 16 10 10
HPI 1 1 0 0
McBSP 2 2 1(SPI) 1(SPI)
12C 2 2 0 0
GPIO 2 2 2 2
GPIO Pins 32 32 24 24
Timer 2 2 2 2
Timer Pins 4 4 0 0
Voltage 1.14-1.32v 1.14-1.32v 1.14-1.32v 1.14-1.32v
Temperature Ta=0 to 70C Tj=95C Ta=0 to 70C Tj=95C Ta=0 to 70C Tj=95C Ta=0 to 70C Tj=95C
Package 272PBGA/208TQFP 272PBGA/208TQFP 144TQFP 1448TQFP
TMX Sample N/A N/A Now 8/2003
TMS MP Now Now 9/2003 9/2003
* Clock speeds are measured in commercial temperature range (-40 ~ 85C)
 
 
 
NeoFidelity, Inc.
Address: #1009, Ace Twin Tower 2, 212-30, Guro-dong, Guro-gu, Seoul 152-766 Korea
Copyright ¨Ï 2004 NeoFidelity, Inc. Email: info@neofidelity.com, Tel: +82.2.6675.1100